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Sunday16 December 2018

Intel Outstanding Leadership Award

NOVATTE has received the “Outstanding Leadership in Vertical Design Win 2012” Award from Intel Channel Partner Premier Program, established and prestigious recognition from Intel. 

Award Intel

The award winner was determined among all Intel Platinum Partners in APAC, including South East Asia, India, Australia, New Zealand and Japan. The winners of Intel Channel Partner Premier Program Awards were presented in Bali, Indonesia, at Intel Solutions Summit APAC 2012 by Kamil Hasan, Director of Intel’s Reseller Channel Organization in Asia Pacific, and Steve Dallman, Vice President of Intel’s Sales and Marketing Group General Manager, Worldwide Reseller Channel Organization. 

The “Outstanding Leadership in Vertical Design Win by Intel” award is an annual award recognizing the company that demonstrates the best in class product performance resulted in substantial return on investment (ROI) to the end-user. Awarded solution was NOVATTE C10K HPC Cluster systems designed and shipped for Financial Services Institution.

NOVATTE is the Singaporean supercomputer manufacturer. NOVATTE delivers customized High Performance Computing systems for Financial Services Industry, scientific researchers, software developers and HPC application users who require low-latency, high performance and reliability. Fine-tuning systems to specific needs and industry verticals, NOVATTE allows its customers to gain drastic competitive advantage in performance, CAPEX savings, operating cost savings and reliability over the peers who use standard boxed solutions widely available on the market. 
Unique Admin-friendly (c) approach, industry leading price, flexibility and fastest deployment and support differentiates NOVATTE as the leading HPC provider in the Asia Pacific region.

About Intel
Intel (NASDAQ: INTC) is a world leader in computing innovation. The company designs and builds the essential technologies that serve as the foundation for the world’s computing devices. Additional information about Intel is available at newsroom.intel.com and blogs.intel.com

Xeon Phi based HPC

Introducing Xeon PhiTM coprocessors Intel is starting a new era in Supercomputing. Working closely with Intel for several months prior to Xeon Phi announcement we were happy to launch P10K Xeon Phi based Cluster and Xeon Phi servers the same day Intel announcement was made. 

Xeon Phi coprocessors are build on established CPU architecture and programming concept to provide the benefits of code re-use to developers of highly parallel applications. Common programming models for Intel Xeon processors extend to Intel Xeon Phi coprocessors, so as developers embrace high degrees of parallelism, they don’t need to rethink the entire problem.


The same techniques that deliver optimal performance on Intel Xeon processors—such as scaling applications to cores and threads, blocking data for hierarchical memory and caches, and effective use of SIMD—also apply to maximizing performance on Intel Xeon Phi coprocessors.

In other words if your code is well parallelized on multiple CPU cores, you just recompile it using Intel corresponding compiler and get an instant speedup of up to 70% per each Xeon Phi card.


5 reasons to consider switching to Intel E5-2600 series CPUs starting from yesterday

On Mar 6, 2012 Intel announced new server CPUs for dual-CPU platform – Sandy Bridge E5-2600-series in which by adding just 2 additional cores it made E5-2600 almost 2 times faster than the previous X5600 generation! How did they do it and why one should consider switching to E5-based system?

Architecture difference between X5600 series and E5-2600 series



How to calculate peak theoretical performance of a CPU-based HPC system

Updated on November 3, 2014

To calculate peak theoretical performance of a HPC system we first need to calculate peak theoretical performance of one node (server) in GFlops and than just multiply node performance on the number of nodes your HPC system has.

HPC world is using the following formulae for node peak theoretical performance:

Node performance in GFlops = (CPU speed in GHz) x (number of CPU cores) x (CPU instruction per cycle) x (number of CPUs per node)

Where to take a number of CPU instructions per cycle:
- Intel X5600 series CPUs and AMD 6100/6200/6300 series CPUs have 4 instructions per cycle
- Intel E5-2600v1 and E5-2600v2 series CPUs have 8 instructions per cycle
Intel E5-2600v3 series CPUs have 16 instructions per cycle (as E5-2600v3 series CPUs have AVX2.0 and FMA instruction sets that at their theoretical maximum are two times lager than that of E5-2600v1 and E5-2600v2)


Example 1: Dual-CPU server based on Intel X5675 (3.06GHz 6-cores) CPUs:
3.06 x 6 x 4 x 2 = 144.88 GFLOPS

Example 2: Dual-CPU server based on Intel E5-2670 (2.6GHz 8-cores) CPUs:
2.6 x 8 x 8 x 2 = 332.8 GFLOPS
(Note that the number of instructions per cycle for E5-2600v1 and E5-2600v2 series CPUs is equal to 8)

Example 3: Dual-CPU server based on Intel E5-2690v3 (2.6GHz 12-cores) CPUs:
2.6 x 12 x 16 x 2 = 998.4 GFLOPS
(Note that the number of instructions per cycle for E5-2600v3 series CPUs is equal to 16)


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